How to generate Schematic Diagram from VHDL Code?
Designers can generate Schematic Diagrams from VHDL codes by using Convert VHDL code to diagram Tool in Schematic Editor
Step 1: Convert VHDL code to diagram tool can be evoked from Schematic Editor | Tools.
Step 2: In Convert VHDL code to Schematic Diagram window, you can set up the truth table entity as shown in figure below and click on Next Button.
Step 3: Click on Next Button will prompts you to VHDL Editor. For example if you are writing VHDL code for full adder the code is as shown in figure below.
Step 4: After coding click on Compile 
. Process wirelist window appears as shown in figure below .
Step 5: Set the parameters and click on Finish button. The diagram will get tagged to the cursor, place the diagram in the suitable position on work sheet.
Checking the functionality of the diagram
Step 1: Evoke Mixed Mode Simulator from Schematic Editor | Preferences.
Step 2: Assign clock patterns on input nets by using clock generator patterns. You can evoke Clock Generator from Tools | Instruments 
| Preset Logic State 
| Clock Generator 
.
Step 3: Place the wave form patterns on input and output nets from Tools| Instruments | Set wave form contents 
| logic wave form 
.
Step 4: Preprocess the circuit from Simulation tools| Preprocess 
.
Step 5: Set the parameters for Transient Analysis from Simulation tools | Analysis 
.
Step 6: Run the Analysis and Check the output wave form.
